The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.)

Circuit Description

A transmission-gate variant of the CMOS tri-state buffer.

The buffer shown here consists of a standard CMOS inverter following by a CMOS transmission gate. AS a consequence, the output of the gate is the inverse of the data input while the transmission-gate is enabled (conducting), and floating whenever the transmission-gate is disabled.

Again, the simulation model of the t-gate only uses the positive control-input, while actual t-gate require both the positive and the negated control-input. An extra inverter might be required to generate the inverted control input.