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CMOS D-type transmission-gate flipflop

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Circuit Description

A switch-level demonstration of the CMOS transmission-gate rising-edge triggered D-type fliplop, shown as a simplified gate-level schematics. See the previous applet for the transistor-level schematics of this circuit and the detailed explanation.

Click the input switches or type the 'c' and 'd' bindkeys to control the clock and data inputs.

Print version | Run this demo in the Hades editor (via Java WebStart)
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Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/dff2.html