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CMOS three-input NAND3 gate

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Circuit Description

This applet demonstrates the static two-input and three-input NAND gates in CMOS technology. Click the input switches or type the ('a','b') and ('c','d','e') bindkeys to control the gates.

The three-input NAND3 gate uses three p-channel transistors in parallel between VCC and gate-output, and the complementary circuit of a series-connection of three n-channel transistors between GND and gate-output.

  NAND3            

  A  B  C  |  Y   
-----------+----
  0  0  0  |  1
  0  0  1  |  1
  0  1  0  |  1
  0  1  1  |  1
  1  0  0  |  1
  1  0  1  |  1
  1  1  0  |  1
  1  1  1  |  0

Print version | Run this demo in the Hades editor (via Java WebStart)
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German)
Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/nand3.html