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adders and arithm...
LFSR and selftest
I/O and displays
CMOS circuits (sw...
XOR (mux tgate)
SRAM (4x1 bits)
Mips R3000 cosimu...
Intel MCS4 (i4004)
image processing ...
[Sch04] RALU, Min...
|CMOS 4x1 bit SRAM
This applet demonstrates the switch-level simulation
of a 4x1 bit CMOS SRAM.
Click the input switches or type the following bindkey to control the simulation: 'a' and 'b' to control the address lines A0 and A1, 'd' to control the data input value, and 'e' to enable the input tristate-drivers.
The applet includes four 6-transistor memory cells, organized as a static random-access memory with four words and 1-bit per word. Depending on the selected (A1,A0) address, one of the four horizontal wordlines is enabled. The corresponding memory cell is then connected via the n-channel pass-transistors to the vertical bitlines. For electrical reasons, all cells are connected by two bitlines, with the bitline on the left of the cell carrying the original memory data, while the bitline to the right of the call carries the inverted data.
When the (active low) write_enable input is activated, the strong input tristate buffers are enabled, and any previous memory data of the currently addressed memory cell is overwritten with the current data input value.
Once data has been written to a memory cell, the write_enable line can be deactivated (high), which in turn disables the input tristate buffers. The bitlines are now driven by the cross-coupled inverters inside the addressed memory cell. In the applet, the value of the positive bitline (left of the cell) is then used as the output of the SRAM. In an actual SRAM circuit, extra (differential) amplifiers are used to generate a strong output signal from the weak signals on both bitlines.
Further reading: Please also check the several gate-level SRAM applets in the memories chapter.
|Print version | Run this demo in the Hades editor (via Java WebStart)|
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