CMOS OAI31 or-and-invert complex gate


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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... inverter, bu... NAND, AND NAND3 NOR, OR NOR3 AOI22 comple... OAI31 comple... TRIBUF tri-s... TGATE TRIBUF (tgate) MUX21 (tgate) XOR (mux tgate) XOR (tgate) DLATCH (tgate) DLATCH (schema) DFF (tgate) DFF (schema) 6T-SRAM cell SRAM (4x1 bits) RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		CMOS OAI31 or-and-invert complex gate The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description The OAI31 complex gate. Click the input switches or type the ('a','b','c', and 'd') bindkeys to control the circuit. The complex gate shown here implements a logical or-and-invert function, namely Y = NOT( (A \| B \| C) & D )

		Print version \| Run this demo in the Hades editor (via Java WebStart)

		Usage \| FAQ \| About \| License \| Feedback \| Tutorial (PDF) \| Referenzkarte (PDF, in German)

Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/oai31.html


		TAMS / Java / Hades / applets: contents \| previous \| next


Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... inverter, bu... NAND, AND NAND3 NOR, OR NOR3 AOI22 comple... OAI31 comple... TRIBUF tri-s... TGATE TRIBUF (tgate) MUX21 (tgate) XOR (mux tgate) XOR (tgate) DLATCH (tgate) DLATCH (schema) DFF (tgate) DFF (schema) 6T-SRAM cell SRAM (4x1 bits) RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		CMOS OAI31 or-and-invert complex gate The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description The OAI31 complex gate. Click the input switches or type the ('a','b','c', and 'd') bindkeys to control the circuit. The complex gate shown here implements a logical or-and-invert function, namely Y = NOT( (A \| B \| C) & D )

		Print version \| Run this demo in the Hades editor (via Java WebStart)

		Usage \| FAQ \| About \| License \| Feedback \| Tutorial (PDF) \| Referenzkarte (PDF, in German)

Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/oai31.html