Wait-Intervals


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Hades Applets contents visual index introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories programmable logic state-machine editor misc. demos I/O and displays DCF-77 clock DCF-77 clock shifter loadable cou... loadable cou... wait-intervals wait-counter decoder FSM relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS		Wait-Intervals The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.) Circuit Description The WaitIntervals block to generate control signals for the decoder state-machine. It takes a six-bit binary input value and calculates three output signals: is_14_to_16 is high if the input value is between 14 and 16; is_34_to_36 is high if the input value is between 34 and 36; larget_than_36 is enabled if the input value is greater than 36. Given the decoder state-machine clock of 20 Hz, these values correspond to actual times of 0.7..0.8 seconds, 1.7..1.8 seconds, and more than 1.8 seconds. There values are used by the decoder state-machine whether the wait interval between detected clock-impulse was one second (normal pulse), two seconds (minute start), or a timeout (no signal).

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Impressum		http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/45-misc/80-dcf77/WaitIntervals.html