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Circuit Description

A six bit synchronous counter connected to the 'WaitIntervals' subdesign.

This counter is used by the 'DecoderFSM' state-machine to calculate the delay between the DCF-77 signal pulses. It is clocked with the 20 Hz clock signal, and reset whenever the decoder state-machine detects a new pulse.

The three output signals generate by this subdesign correspond to 'one second' interval between pulses, 'two seconds' interval between pulses, and 'timeout' or 'missing signal'.

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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/45-misc/80-dcf77/WaitCounter.html