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Circuit Description

This applet demonstrates a three-stage Micropipeline built from Muller C-gates.

Click the write switch twice to generate a 0-1-0 pulse on the write input. This fills a '1' bit into the rightmost free position of the micropipeline. Repeat this until the full status line remains high when you release (low) the write input line.

Now click the read switch twice to generate a 0-1-0 pulse on the read input line. This removes the rightmost '1' bit from the micropipeline. Repeat until the available bit remains low (inactive).

You can now mix write and read transitions and watch how a partially filled micropipeline behaves.

Unlike traditional clocked FIFO (first-in-first-out) buffers, the micropipeline does not need a clock input signal or global synchronization. Each pipeline stage manages its own synchronization with its left and right neighbors. As such, micropipelines form an interesting building block for asynchronous circuits.

For details, please check the original papers:

• I. E. Sutherland, Micropipelines, Commun. ACM, vol. 32, no. 6, pp. 720--738, June 1989
• Robert F. Sproull, Ivan E. Sutherland, Charles E. Molnar. The Counterflow Pipeline Processor Architecture, IEEE Design and Test of Computers, vol. 11, no. 3, pp. 48-59, July/September 1994.

Note: the initialization of micropipelines (and asynchronous logic with handshake protocols in general) is notoriously difficult. The C-Gates used here silently include their own power-on-reset circuitry to guarantee that all gates start in the low state at the start of the simulation.