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D-type flipflop with enable-input

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Circuit Description

The D-type flipflop with enable-input consists of a multiplexer in front of a standard edge-triggered D-type flipflop (left part of the applet).

Depending on the value on the enable signal E, the multiplexer passes the value from the external data input D or the feedback value from the flipflop output Q through to the flipflop data input. At the rising edge of the clock input C, the flipflop will load either the current external data input value D (when E is high), or re-load its current value Q (when E is low). As usual, the asynchronous reset input R allows to reset the flipflop. (Note that the extra inverter in front of the mux control input is only used to make the schematics a little bit cleaner. In practice, one could toggle the mux inputs and avoid the extra inverter.)

To control the simulation, click the input switches or type the 'r' (reset), 'c' (clock), 'd' (data-input), and 'e' (enable) bindkeys.

At first glance, the much simpler circuit shown on the right seems to perform the same function. Here, both the clock signal X and the enable input Y are gated by a single AND-gate. Obviously, the flipflop will only load a new value from the data-input when the enable-input Y is high during the rising edge of the clock X.

Unfortunately, this circuit is sensitive to hazards on the X and Y inputs, and can only be used when the X and Y inputs are proven to be hazard-free. For example, whenever the clock-input Y is being held high, a single 0-1-0 hazard pulse on the X enable input will also trigger the flipflop to load a new (and spurious) data value.

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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/16-flipflops/20-dlatch/dff-enable.html