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LSSD level-sensitive scan design latch

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Circuit Description

This applet shows the so-called LSSD D-type latch. The level-sensitive scan design technique was developed and pioneered by IBM, and forms the basis for a structured approach to the design of testable circuits.

Click the input switches, or type the 'd', 'c', 'i', 'a' bindkeys to control the data, clock, shift-in, and shift-enable inputs of the circuit.

The latch shown here has the usual data input D and clock input CLK. It also has a second set of inputs I and A, where A functions as a separate clock input (shift-enable) and I acts as a second data input (shift-in). In standard operation, I and A are held low, and the circuit operates like a standard D-type latch.

For shifting data, C and D are held low, and the latch is loaded via the I input and clock-pulses on the A signal.

For a detailed description, see chapter 7.3.3 of Weste and Eshragian, Principles of VLSI design.

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