Hades logoHades applet banner
Clocked SR-flipflop (AND-NOR)

applet icon

The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.)

Circuit Description

A simple clocked SR flipflop built from AND-gates in front of a basic SR flipflop with NOR-gates.

Obviously, the values at the R and S inputs are gated with the clock signal C. Therefore, as long as the C signal stays at 0 value, the flipflop stores its value. On the other hand, the flipflop behaves like the standard SR flipflop while C is 1.

Because the behavior is controlled by the static level of the clock signal, such flipflops are called level-sensitive or latches.

(Implementation note: in order to avoid flipflop oscillations due to the discrete-event based simulation model when the 'forbidden' input values (111) are selected, the gate-delays of the first-level AND gates are set to different values. Due to this choice, the reset state is preferred. The real flipflop would enter a random state based on the current operating parameters like temperature, etc. )

Print version | Run this demo in the Hades editor (via Java WebStart)
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German)
Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/16-flipflops/10-srff/clocked-srff.html