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Counter-based pulse-generator

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Circuit Description

This applet shows the pulse-generator sub-component required used in the frequency counter (see the previous applet).

The circuit consists of a NOR-gate RS-flipflop and a six-digit asynchronous decimal counter, built from 74390 integrated circuits. To avoid unnecessary repaints during simulation, no displays are used in this applet. Please see the description of the previous applets for details about the 74390 counter component and the decimal-carry logic via the AND-gates.

Pressing the 'start' switch will set the RS-flipflop and enable counting of the reference clock pulses. The output of the RS-flipflop is the 'gate' impulse (used to control the measurement-counter of the frequency counter). The NOR-gate RS-flipflop is reset when the counter value reaches the value 1000000 (one-million). Given the reference clock-generator period of 1.0E-5 seconds, the output interval is exactly 1.00000 seconds.

Note that the pulse-generator only works as long as the 'start' switch is reset before the counter overflows. Please make sure to press the 'start' switch off again soon enough after starting the counter. In a 'real' pulse-generator, extra logic would have to be used to ensure this condition.

Print version | Run this demo in the Hades editor (via Java WebStart)
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German)
Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/30-counters/70-ttl/one-second.html