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TTL-series 7490 decimal counter

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Circuit Description

This applet shows the internal structure of the TTL-series 7490 1:10 counter integrated circuit.

The counter consists of a first stage based on a single JK-flipflop (1:2) and a second state of two D-flipflops and one JK-flipflop (1:5).

Note that the integrated circuit provides two reset-inputs R0(1) and R0(2) and two separate set-inputs R9(1) and R9(2), which allow setting the counter to values zero (0b0000) and nine (0b1001) respectively. As the Hades flipflop library does not include a JK-flipflop with reset and preset inputs, the flipflops from the TTL-series 7476 JK-flipflop circuit are used here.

For the full decimal 1:10 counter, the output of the first stage QA is connected to the clock input nB of the 1:5 counter stage.

Larger (asynchronous) decimal counters can be built by a cascade of multiple 7490 chips. The 74390 circuit contains two 7490 counters (without separate preset inputs).

Print version | Run this demo in the Hades editor (via Java WebStart)
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Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/30-counters/60-ttl/SN7490.html