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Frequency Divider (D flipflops)

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Circuit Description

This circuit implements an asynchronous 8-bit counter using D-flipflops.

Each stage of the counter consists of a standard D-flipflop, with the data-input driven by the negated output of the flipflop. Therefore, the flipflop changes its state ('toggles') on each rising-edge of the flipflop clock input. A few textbooks introduce a special flipflop type for this, called toggle-flipflop or TFF.

The data output of stage n generates the clock input for stage n+1. Therefore, the individual stages of the counter do not change state at the same time, but rather one-after-another.

Obviously, an asynchronous counter is very cheap - no extra gates are required beyond the flipflops. Also, an asynchronous counter is very fast, because no dependencies between the stages exist. However, when using asynchronous counters as a part of a larger synchronous (clocked) system, great care must be taken to ensure that the counter value is stable before reading and using it.

One important application of asynchronous counters is as a frequency divider, where only the last output of the counter cascade is used - usually, as the clock input to the following block of logic. Therefore, the asynchronous nature of the counter is not critical, as the individual outputs of the intermediate stages are not used at all.

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Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/30-counters/20-async/counter-dff.html