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Basic half-adder and full-adder circuits

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Circuit Description

The basic 1-bit half-adder and full-adder circuits. The sum bit is calculated with XOR gates, while the AND gates are used to check whether two (or more) inputs are 1, which implies that the carry out bit must be set.

Click the input switches, or use the ('a','b','c') and ('d','e') bindkeys to toggle the input values of the full- and half-adders.

Note that the carry calculation path shown in this applet uses the direct AND-OR realization (because it is the easiest to understand). However, as will become clear in the following applets, the speed of the carry generation logic in large adders is often performance critical. Therefore, cheaper and faster implementations based on inverting gates (NAND-NAND), complex gates, or even custom designed special circuits are used in practice.

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Impressum http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/20-arithmetic/10-adders/halfadd-fulladd.html