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Circuit Description

A demonstration of the generic RTLIB read-only memory component with separate active-low chip-select and output-enable control signals (class hades.models.memory.ROMoe).

The ROMoe memory uses tri-state outputs controlled by the (active-low) output-enabled control signal, so that the memory output can be connected directly to the data-bus driven by multiple components. The RTLIB also includes the basic ROM and ROMcs classes for read-only memories without further control inputs, and with chip-select input respectively.

The image below shows a screenshot of the ROM applet with open memory editor window; note that the memory cell that was last accessed is highlighted in green (here, address 0x23):

Use the several menu commands of the memory component to specify the memory size (number of words, bits per word), to load and save memory data from and to files, etc. Note that the memory editor will not fully update its user-interface when you change the memory size (this is a known but minor bug). Please close and re-open the design file to re-initialize the memory editor with the new memory size.