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Circuit Description

This applet demonstrates the standard read-cycle used to read the RAM memory contents.

When the applet is first loaded by your browser, the animation sequence starts automatically. It stops (pauses) the simulator once the animation is finished. Press the play button in the simulator control panel to continue with an interactive simulation (click the switches), or click the stop (rewind) and play buttons to re-start the animation sequence from the beginning.

The animation sequence also opens the waveform viewer. Depending on your operating system and window manager, you might have to move the waveform viewer window to the background in order to see the animation. After the animation has stopped, press the zoom fit button (or type the f bindkey) in the waveform viewer window to look at the timing of the write-cycles.

When you start the simulation, the RAM is still un-initialized and all memory cells hold the 'X' (undefined) value. After two seconds, the same write sequence already used in the previous write-cycle applet is executed to initialize the RAM with the values 001b, 0010b, 0111b, and 1000b. However, this time the delay between the individual is set to 1 msec instead of 1 sec. This means that the write cycles complete almost immediately, but you can later zoom into the waveforms to observe the details.

Once the RAM contents is initalized, the animation de-asserts the nChipSelect input and the RAM will tri-state its outputs. After a few seconds, the address input is set to 00b, and nChipSelect is activated (active low). The RAM now outputs the contents of the selected memory cell (here 0001b) to its data output ports.

The following steps of the animation simply change the address inputs of the RAM in the order 00b, 01b, 10b, 11b, and repeat this sequence. As soon as the address changes, the address-decoder inside the RAM activates another wordline, the corresponding memory cells are activated, and their values propagate via the output bitlines and the output tri-state buffers to the RAM data output ports. The time required for the whole process is the specified read-access time of the RAM. Note that there is no nead to switch the nChipSelect or nWriteEnable lines during this read operations; changing the address is enough.