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RAM tri-state bitline buffer

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Circuit Description

This applet shows the bitline buffer circuit used in the RAM circuit.

The nWE (active-low write enable) signal controls the tri-state buffer that drives the bitline. While nWE is high, the tri-state buffer is disabled and the bitline is not driven. When nWE is low, the data input is driven onto the bitline.

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Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/40-memories/40-ram/ram-bitline-buffer.html