Applets
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introduction std_logic_1164 gatelevel circuits delay models flipflops adders and arithm... counters LFSR and selftest memories
programmable logic
PLA circuit GAL output cell GAL demo 1 GAL demo 2 GAL demo 3 GAL demo 4 ACT1 cell ACT1 AND3 gate ACT1 XOR2 gate ACT1 SR-flip... state-machine editor misc. demos I/O and displays DCF-77 clock relays (switch-le... CMOS circuits (sw... RTLIB logic RTLIB registers Prima processor D*CORE MicroJava Pic16 cosimulation Mips R3000 cosimu... Intel MCS4 (i4004) image processing ... [Sch04] Codeumsetzer [Sch04] Addierer [Sch04] Flipflops [Sch04] Schaltwerke [Sch04] RALU, Min... [Fer05] State-Mac... [Fer05] PIC16F84/... [Fer05] Miscellan... [Fer05] Femtojava FreeTTS
Circuit Description
This circuit demonstrates two more examples of logical functions using the GAL or generic array logic structure. For a description of the circuit structure see the previous two applets.
In this demonstration, the output enable of the output cell blocks is set to low, enabling the tristate driver. Also, the XOR bit of each output cell is selected, so that the direct (non-inverted) output of the OR-gates is passed through to the Y_out output. Additional external inputs C and D have been added (on the right of the schematics), feeding back into the AND fuse matrix.
The programming in the upper GAL block implements the logical function (AB + AC + BC), resulting of the ORing together of the three terms (AB), (AC), and (BC) from the first, second, and third rows of the fuse matrix. (Keeping both the A and /A fuses intact in the fourth row results in a constant zero value for that row).
The programming of the lower GAL block implments the XOR function of inputs A and B.
+ = fuse ok
. = fuse blown
A /A B /B C /C D /D function
+ . + . . . . . A AND B
+ . . . + . . . A AND C
. . + . + . . . B AND C
+ + . . . . . . zero
total:
AB or AC or AD
+ . . + . . . . A AND /B
. + + . . . . . /A AND B
. . . . . . + + 0
. . . . . . + + 0
total: A xor B