Hades logoHades applet banner
AND and NAND gates

applet icon

The image above shows a thumbnail of the interactive Java applet embedded into this page. Unfortunately, your browser is not Java-aware or Java is disabled in the browser preferences. To start the applet, please enable Java and reload this page. (You might have to restart the browser.)

Circuit Description

A demonstration of varous AND logic gates. Click the input switches to toggle the corresponding input value between 0 and 1, and watch the resulting behaviour. You can also use shift+click to toggle the input value between the states 0, 1, Z (tri-state, not driven) and X (undefined). The default input values of the switches are chosen so that the first mouse-click already changes the output value of the corresponding gate.

The left column includes the non-inverting gates ('positive logic'), namely the one-input buffer, and the AND gates with two, three, and four inputs. The right column shows the inverting gates: inverter and NAND gates with two, three, and four inputs. While the non-inverting gates seem more intuitive, most current technologies are actually based on the inverting gates. For example, in CMOS technology the non-inverting gates are actually realized by the inverting gate followed by an inverter.

Naturally, it is easy to define logic gates with more than four inputs, but these are rarely used in practice due to technological restrictions. While bipolar technology might allow gates with perhaps up to about six inputs, most MOS techology libraries only include AND and NAND gates with up to four inputs. When gates with more than four inputs are required, a cascade of multiple smaller gates is used. Click here for the demonstration of a 12-input AND gate.

For interactive switch-level (transistor-level) demonstrations of CMOS gates vist our CMOS technology demonstration page. Obviously, the implementation of multiple input logic gates requires a series-connection of the corresponding number of transistors. Once more than three or four transistors are connected in series, it is difficult to guarantee that the gate output voltages remain inside the voltage ranges that define the logical levels. Additionally, the capaticance of the series-connected transistors increases with each level, which reduces switching speed. Typically, only three- or four-input gates are used in CMOS technology.

To explore the circuit, just click the corresponding switches, or type the following keys:

  • a (buffer)
  • b (inverter)
  • s,d (AND2)
  • f,g (NAND2)
  • w,e,r (AND3)
  • u,i,o (NAND3)
  • 1,2,3,4 (AND4)
  • 5,6,7,8 (NAND4)
(If typing the bindkeys does not work, please use one initial mouseclick into the applet, to ensure that the simulator has the keyboard focus).

Note: As can be seen in the applet, the one-, two-, and three-input gates in Hades have connections (=ports) with the same spacing, actually 1/4th of an inch. On the other hand, the input ports of the four-input gates are positioned on coordinates that are a multiple of 1/8th inch. You will have to change the editor settings (view->magnetic->grid->1/8th) in order to use those gates in the editor.

Print version | Run this demo in the Hades editor (via Java WebStart)
Usage | FAQ | About | License | Feedback | Tutorial (PDF) | Referenzkarte (PDF, in German)
Impressum http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/and.html