Fachbereich Informatik

Models and Packages

Our collection of public-domain VHDL models and packages. If you cannot find a model here, please make sure to check the other VHDL servers.

Packages | Microprocessors | Memory | Misc.


Standardized packages, as part of the IEEE Standards, are not free and have to be bought from the above address. The following packages are either draft standards and proposals from the working groups or free (vendor specific) packages. Please see and respect the copyright notice inside the files.

Before download, please check your tool- or vendor-specific documentation, since most tools have the standard packages already included. Often they use specialized versions, which are optimized with respect to the internal algorithms.


SoftCores A private website with four synthesizable microprocessor cores: PPX16 (PIC16C55, PIC16F84), T80 (Z80), T51 (8051), and AX8 (90S1200, 90S2313). The site also offers some utilities, including a converter from Intel Hex and Motorola S-Record files to VHDL ROM descriptions, and a tool to read and write synchronous serial (I2S) data to files.
HC11 core Both behavioural and RTL source code for the HC11 microcontroller core from Green Mountain Computing Systems. Not surprinsingly, makefiles and project files are optimized for their own VHDL simulator.
8051 MCU A new 8051 MCU IP core under LGPL license, co-developed by Oregano Systems and the University of Wien. The model is synthesizable, fully synchronous, and includes timer and UART interfaces.
mc8051 Both behavioural and structural (synthesizable) models of the 8051 µController, with memory blocks but without peripherial devices. The model comes with testbench and several .hex files.
i8051 Another synthesizable model of the 8051 µController core (without interrupt handling). Includes ROM and RAM blocks but no peripheral devices. The model comes with several test programs.
PIC 16C5x A structural model of the PIC16C5x microcontroller under the GNU public license from Ernesto Romani (romani@ascu.unian.it). The model has been synthesized to a Xilinx 4005 FPGA and comes together with a tool to convert assembler code to a VHDL ROM model.

compressed tar archive (267K, structural VHDL model, assembly packer, some documentation)

Check www.microchip.com for datasheets, documentation, and (free) tools for the PIC series of microcontrollers.

A VHDL simulation model of the ERC32, a radiation tolerant SPARC processor for space applications, complete with documentation and makefiles for the Synopsys and Model Tech simulators.

All models are fully functional with parametrisable timing. The source code and data sheets for the models are provided for free (GNU license) via the ERC32 home page: ERC32 WWW-Server.

The processor consists of integer unit, floating-point unit and memory controller. IU and FPU are compatible with the Cypress 76C01 and 76C02 Sparc V7 processors.

The LEON processor is a synthesizable implementation of the SPARC-V8 architecture, distributed under the LGPL license. The processor includes a five-stage integer pipeline and an AMBA-style bus with several peripherial blocks. The LEON source code is also an interesting example of using VHDL data types and generics for model configuration. The processor has been sythesized to several target libraries, as well as Altera and Xilinx FPGAs.
DLX Both behavioral and RT-level model of Hennessy and Patterson's generic 32bit RISC-processor architecture (without instruction pipeline, however).
compressed tar archive (37K, VHDL description and two simple programs).
directory with the uncompressed files.
SuperScalar DLX SuperScalar DLX:
A PPC603-style superscalar mixed behaviour/RTL model of the DLX processor from the TU Darmstadt, Germany:
  • superscalar, pipelined implementation of DLX (but without floating-point)
  • 4 separate functional untis: branch-resolve, arithmetic-logical, multiply-divide, load-store
  • 5-entry reorder buffer, up to 5 active instructions
  • 4-entry branch-target-buffer
  • precise exceptions
  • small 64-entry I-cache and D-cache
The link above contains documentation, all VHDL models, and some test programs in ZIP format. The VHDL code itself is nicely commented and very readable.
GL85 GL85: This circuit is an op-code compatible clone of the i8085 8-bit microprocessor:
6502 A behavioural (but synthesizable) model of the 6502 microprocessor from the Free-IP site.
i80386 A simple (and incomplete) behavioral model of the Intel 80386 microprocessor (58K ASCII).
m68000 A simple (and incomplete) behavioral model of the Motorola 68000 microprocessor (36K ASCII).
AMD 2901 AMD 2901 bit slice(Unix .tar.gz)
AMD 2910 bit slice(Unix .tar.gz)


A simulation model for the 24Cxx series of I2C EEPROMs from M. Neumann used for verification of a I2C-master.
and Testbench
Another I2C EEPROM simulation model with timing checks and file dump/load mechanism, together with a procedural testbench simulating an I2C-master.
SRAM, full timing Our generic SRAM model with full timing, by A. Klindworth. The model uses generic parameters for timing and size, timing checks, startup initialization from file, memory dump to file, etc.
SRAM, no timing A simple model of a 64Kx8 SRAM without timing, but with startup initialization from a file.
DRAM A DRAM model by Shannon Hill (posted to comp.lang.vhdl)
EPROM, no timing A simple 64Kx8 EPROM model without timing checks, but with an Intel-HEX file parser for initialization.
Vendor memory models Today, several memory vendors offer VHDL simulation models for their products. For example, Micron Technology offers downloadable (but licensed) simulation models for several memory products, including double data rate SDRAM and SGRAM.

Misc. & Cores

Note that some of the files listed in this section are demo versions or behavioural versions of otherwise commercial products. They are listed here among fully free software because they implement important and useful cores - e.g. PCI or USB controllers.
Jane neural network processor VHDL and Verilog sources for a programmable neural network processor by Suresh Kumar. The download consists of a ~2MByte archive file which contains the source files and documentation. See the "Guide/About.html" file in the archive file for an overview.
USB core While the (synthesizable) USB controller core itself is a commercial product, Trenz electronic provides the behavioural model and testbenches under GNU licence for free (see the "free downloads" link.) They also offer a clone of the MCS51 microcontroller.
Free-DES A synthesizable core for DES encryption from the Free-IP site.
CRC LFSR A cyclic-redundancy-check feedback shift-register, by Russ DeHoedt (posted to comp.lang.vhdl)
MCNC circuits The standard CAD-benchmark circuits of the MCNC (ftp.mcnc.org).
FPGA course A collection of circuits and testbenches for our recent FPGA lab. course, which uses Altera FPGAs. For example, you will find another SRAM model and a component to convert ASCII-strings into RS232 (8N1) format. Irdafuse is a circuit to protect an IrDA tranceiver from accidental overload during testing of student's designs.
FFT A synthesizable model of a FFT generator together with a full description (420KB PDF). From the author's submission mail: The design of the processor was taken from an IEEE workshop report. The report detailed a 256-point FFT I have limited mine to an 8-point FFT for easier debugging, which obviously cannot be used as such, since its accuracy would be poor. Neverthless all the features of the processor are present and upgrading it to a 256 point processor is easy.
Bidirectional delay
The model of a bidirectional connection, simulating line reflections for passive (off-switched) drivers from M. Neumann.