RAM (random access memory) structure

Description

This applet demonstrates the internal organization of a typical random access memory (RAM). The RAM consists of four main parts, namely

• the memory matrix, built as a 2D-array of 1-bit storage cells,
• the address decoder,
• the input buffer and amplifiers
• the output buffer and amplifiers.

Just play with the RAM inputs (address, data, nChipSelect, and nWriteEnable) and try to write data to the memory cells. You can also check the next three applets for predefined animation sequences:

• standard write-cycles
• standard read-cycles
• fast write-cycles

• single bit memory cell (latch)
• address decoder
• bitline buffer

In order to minimize the chip size of the RAM, a very small size of each storage cell and an efficient layout and signal routing in the memory matrix is essential. One obvious choice is the use of orthogonal wires to access the memory. The wordlines run horizontally and are enabled to select one word of memory data. The bitlines run vertically and are connected to storage cells of different memory address. In the applet, two separate bitlines are used for each data bit. The left bitline of each pair is used to write data into the storage cell selected by an active wordline, while the right bitline is used to read the data. The RAM shown in the applet stores 4 words of 4-bit each (a 4x4 bit RAM). For each cell, an extra LED is used to visualize the data currently stored in the cell (undefined, 0, or 1).

The two most important types of RAM differ in the choice of the storage cell. In principle, any type of latch or flipflop can be used to build a static random access memory, this is, a memory whose contents remains stored while the circuit is powered. Perhaps the most frequently used cell, the so-called six-transistor cell is a variant of the standard transmission-gate latch. An interactive applet demonstration of the 6T-cell can be found here. Besides the use of only six transistors to store one-bit of information, the 6T-cell also allows for a very compact routing of signal wires. In dynamic random access memory (DRAM) chips, the storage cell consists of a single NMOS-transistor and a tiny capacitor. A high or low voltage (charge) on the capacitor is interpreted as a logical 1 or 0 value. Due to leakage, the charge on the capacitor has to be refreshed periodically.

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