|
Class Summary |
| And2 |
And2: a 2-input AND gate with user-defined gate-delay "t_delay". |
| And2Vertical |
And2Vertical - subclass of And2 with a vertically oriented symbol |
| And3 |
And3: a 3-input AND gate with user-defined gate-delay "t_delay". |
| And3Vertical |
And3Vertical - subclass of And3 with a vertically oriented symbol |
| And4 |
And4: a 4-input AND gate with user-defined gate delay. |
| And4G |
|
| And4Neg2 |
And4Neg2: 4-input AND gate with normal inputs A,B and negated inputs C,D,
and user-defined gate delay. |
| And6 |
And6: a 6-input AND gate with user-defined gate delay. |
| BitlineBuffer |
BitlineBuffer: a non-inverting buffer that transfers Z into Z. |
| Buffer |
Buffer: simple non-inverting buffer gate. |
| BufferSmall |
BufferSmall: a buffer with a smaller, space-saving symbol. |
| Demux14 |
Demux14: a simple 1-to-4 demultiplexer gate with user-defined delay. |
| GenericGate |
GenericGate - base class to provide common stuff for logic gates. |
| Inv |
Inv: a simple inverter gate with user-defined gate-delay t_delay. |
| InvOpenCollector |
InvOpenCollector: in inverter with open-collector output. |
| InvSmall |
InvSmall - subclass of Inv with a smaller, space-saving symbol. |
| InvSmallVertical |
InvSmallVertical - subclass of Inv with a smaller, space-saving symbol. |
| Mux21 |
Mux21: a simple 2:1 multiplexer gate. |
| Mux41 |
Mux41: a 4:1 multiplexer gate. |
| Nand2 |
Nand2 - a 2-input NAND gate with user-defined gate-delay "t_delay". |
| Nand3 |
Nand3: a 3-input NAND gate with user-defined gate-delay "t_delay". |
| Nand4 |
Nand4: a 4-input NAND gate with user-defined gate delay. |
| NandMetastable2 |
NandMetastable2 - a 2-input NAND gate with user-defined gate-delay "t_delay". |
| NandMetastable3 |
NandMetastable3: a 3-input NAND gate with user-defined gate-delay "t_delay". |
| Nor2 |
Nor2 - a 2-input NOR gate with user-defined gate-delay "t_delay". |
| Nor3 |
Nor3: a 3-input NOR gate with user-defined gate-delay "t_delay". |
| Nor4 |
Nor4: a 4-input NOR gate with user-defined gate delay. |
| Or2 |
Or2 - a 2-input OR gate with user-defined gate-delay "t_delay". |
| Or3 |
Or3: a 3-input OR gate with user-defined gate-delay "t_delay". |
| Or4 |
Or4: a 4-input OR gate with user-defined gate delay. |
| Or6 |
Or6: a 6-input OR gate with user-defined gate-delay "t_delay". |
| Tri |
Tri: a tristate buffer. |
| WeakBuffer |
WeakBuffer: weak non-inverting buffer. |
| Xnor2 |
Xnor2: a 2-input XNOR gate with user-defined gate-delay "t_delay". |
| Xor2 |
Xor2: a 2-input XOR gate with user-defined gate-delay "t_delay". |