Fachbereich Informatik


EPLD Based Transient Recorder


The EPLD based transient recoder VidTrans records and replays color video signals in real time. This allows to transponse short video sequences between real world and computer simulation. It is a bidirectional bridge between real analog video signals and digital video processing devices under developement for example in a VHDL or program environment. This encourages simulations very close to system level conditions of video devices and enables direct evaluation of results. It is also suitable for education as an interface between real world and computer simulation. Control and data transfer is handled via the parallel PC printer port.

Framegrabber Image VidTrans Image
Full Frame - extracted with a commercial hardware frame grabber. Half Frame - extracted with a software frame grabber (C program) from a video data stream recorded by the circuit itself.

The speed of EPLDs available now allows applications in the area of video signal processing. As in the present case, the integration density of current EPLDs makes it possible to realize the transient recorder with few EPLDs and a handful of other components. The relative low effort in realizing a prototype caused by using EPLDs motivates building an EPLD based transient recorder to support simulation in a VHDL environment very close to system level conditions where signals pass through the same components. So, interactions between signals and system environment can be observed by signal exchange between system environment and simulation.


Following animation demonstrates the importance of simulation close to system level conditions: Extraction of a sequence of frames by a C program (CFrame) out of sampled video signal data works well with respect to horizontal synchronization. The vertical synchonization works well with respect to single frames, but defective with respect to the sequence.


'''Where is the bug ...'' (8 Frames)
Extraction of single frames out of a sampled video signal (VIDEO DATA) has been done with a program (CFrame) which stores them in PGM format. These frames have been scaled to 200x150 pixels with xv, stored as GIFs, and rearranged as a sequence of frames using Microsoft GIF Animator.

Such failure could be hidden by viewing just single frames, and would be difficult to discover by inspection of video signal plots. In the present case, the failing behavior is not a result of a bad implementation - but properties of real (an disturbed) video signals have not been taken into account.

Similar problems are possible in digital generation of color video signals. The quality of those signals can be estimated finally inspecting them on a color TV. For example, the exchange of video signals between simulation and real TV helps to approximate the behavior of a digital simulation model of a TV with real ones step by step.

All components of the circuit VidTrans have been described in VHDL and simulated in common on a system level VHDL environment. Besides the synthesizable VHDL models of the both EPLDs, pure behavioral VHDL models of bord components (DRAM, Printer Port, FADC, DAC) have been developed to allow board level simulation. Also the contol program PrnTrans has been integrated into the board level simulation. Communication between control program and the behavioral VHDL model of parallel printer port interface of VidTrans was realized via files. Functional simulation was done with the Synopsys VHDL System Simulator. Mapping the design to EPLDs, we used Altera MAX+Plus II.

Examplary synthesis with the Synopsys Design Compiler, the ES2 ecpd07 as the target CMOS process (0.7µm) and Cadence (DF-II, Cell Ensemble) resulted in pad-limited design with a total area of approximate 3.9mm x 3.7mm with a core area of only 1.0mm x 1.2mm.

Hardware and software have been developed during the PhD activities of Lars Larssson to support the VLSI implementation of a neural network for real time image processing. The circuit has already been used in context of a bachelor thesis (german: "Studienarbeit") in the area of digital video signal processing.

technical Data

EPLDs 2 x Altera EPLD Typ EPM7128ELC84
 shifter 4 x 8 Bit Video Shift Register + 32 Bit Video Buffer
 controller Interface to Video Shift Register + Printer Port + DRAM
 utilization ~ 80 %
 pads 84
FADC Motorola MC10319
VDAC + Video OpAmp 1/3 Brooktree Bt121 + 1/3 elantec EL4393C
system clock frequency 30 MHz
sample frequency 15 MHz
DRAM Memory
4 MBytes (4 x 1 MByte SIMMs)
2400000 Bytes = 8 Half Frames (PAL) = 0,16 s