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Synchronous Up/Down Counter (JK flipflops)

Synchronous Up/Down Counter (JK flipflops) screenshot

Description

A synchronous 4-bit up/down counter built from JK flipflops. Depending on the logic value on the Up/nDown input, the counter will increment or decrement its value on the falling edge of the clock signal. The additional enable input enables (1) or disables (0) counting.

To operate the counter, click the nreset, nclock, enable, and up/down switches, or type the 'r', 'c', 'e', and 'u' bindkeys.

During up-counting, the stage-n flipflop should toggle when all lower flipflops are 1. Therefore, in each stage, one AND gate is used to calculate this carry signal for the next stage flipflop. Similarly, during down-counting, the stage-n flipflop should toggle when all lower flipflops are 0. This is calculated using AND gates connected to the NQ outputs of the flipflops. Each AND gate has one additional input that takes the corresponding up or down enable signal. The outputs of both AND gates are then ORed together to enable the J=K=1 inputs to toggle the JK flipflops.

Exercise: Design the logic required to control the carry-out (or 5th bit) for this counter.

Run the applet | Run the editor (via Webstart)


Impressum | 24.11.06
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/30-counters/40-updown/updown_print.html