TAMS / Java / Hades / **applets** (print version): contents | previous | next#### TTL-series 7485 comparator circuit (4 bit)

**Description**

This applet shows the internal gate-level circuit
used in the TTL-series **7485 4-bit magnitude comparator** ICs.
In the first level of logic, using the NAND and AND-OR-INVERT gates,
the corresponding bits of the A and B inputs are compared.
(This could also have been implemented with XOR gates.)
These signals are then ANDed together with the A=B_in input signal
to calculate the A=B_out signal.

The second, complex looking stage of the schematics acually
consists of two symmetrical circuits, one of which checks for A>B
and the other one for B>A.
The path from the carry/cascade inputs to the outputs
goes through two gates only, resulting in a fast cascade
when many circuits are interconnected.

Run the applet | Run the editor (via Webstart)

Impressum | 24.11.06

http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/20-arithmetic/45-compare/7485-comparator_print.html