hades.utils.vhdl
Class VHDLWriter

java.lang.Object
  hades.utils.vhdl.VHDLWriter

public class VHDLWriter

extends java.lang.Object

export HADES models to VHDL-93 format.

VHDLWriter: a class to export HADES SimObjects to VHDL 93 format. When called with a HADES design, the VHDLWriter will try to construct a netlist (RT-level) architecture of the current HADES design, complete with all subdesigns and SimObjects.

VHDLWriter writes a separate .vhd file for each new subdesign encountered.

When called with a HADES SimObject, the VHDLwriter will try to write a corresponding VHDL architecture for that SimObject - either behavioural or netlist. If the SimObject implements the VHDLexportable interface, the VHDLexportable methods like writeEntity() and writeArchtecture() are called directly.

For a few other SimObjects, the VHDLModelFactory implements methods to write a compatible VHDL-93 behavioural architecture, e.g. for all basic and complex gates, and flipflops. Rtlib-support requires handling of generic declarations and should be available soon.

Otherwise, VHDLWriter tries to construct a VHDL entity declaration from the SimObject's ports and just writes an (empty) dummy architecture and configuration.

Some options of VHDLWriter can be specified via SetupManager properties in the 'hades.cnf' configuration files (please note the default values): However, THIS IS NOT IPLEMENTED YET.

• Hades.VHDL.WorkDirName WORK
• Hades.VHDL.DefaultArchitectureName hades
• Hades.VHDL.DefaultRTArchitectureName netlist
• Hades.VHDL.DefaultFSMArchitectureName fsm
• Hades.VHDL.DefaultConfigurationName default
• Hades.VHDL.dontWritePowerPorts true

The name mapping of Hades SimObject (Java) class name to VHDL names can be specified via an external properties file (third optional command line argument to main()). For example, create a file "my-vhdl-mapping.txt" and put in lines like "hades.models.gates.And2 AND2".

Field Summary

(package private) java.util.Hashtable	architectureTable
(package private) java.util.Hashtable	classmapTable
(package private) java.util.Hashtable	componentDeclTable
(package private) java.util.Hashtable	configurationTable
static boolean	debug
(package private) java.lang.String	defaultArchitectureName
(package private) java.lang.String	defaultConfigurationName
(package private) Design	design
(package private) boolean	dontWritePowerPorts
(package private) java.lang.String	fileName
(package private) java.util.Hashtable	instanceTable
(package private) java.util.Stack	makefileStack
(package private) VHDLModelFactory	modelFactory
(package private) java.util.Hashtable	nameToObjectTable
(package private) java.util.Hashtable	objectToNameTable
(package private) java.io.File	outputDirectory
(package private) java.io.PrintWriter	printWriter
(package private) java.lang.String	resourceName
static java.lang.String	VERSION_ID
(package private) java.util.Hashtable	vhdlFilesTable

Constructor Summary

VHDLWriter()
create a new VHDLWriter for a given Hades Design

Method Summary

static void	dbg(java.lang.String msg)
void	dumpTables()
java.util.Hashtable	getClassmapTable()
java.lang.String	getEntityNameFromClassname(SimObject obj) construct a valid VHDL entity name for a given SimObject or (Sub)Design.
static java.lang.String	getPortDirection(Port port)
static java.lang.String	getPortSignalType(Port port)
static java.lang.String	getSignalType(Signal signal)
static void	main(java.lang.String[] argv) check the VHDL output on the Hades Design specified via file/resource name argv[1] and write to the directory specified in argv[0]
java.lang.String	makeUniqueVHDLName(java.lang.Object obj, java.lang.String objName)
java.lang.String	makeUniqueVHDLName(Signal s)
java.lang.String	makeUniqueVHDLName(SimObject so)
static java.lang.String	makeVHDLName(java.lang.String s) mangle name s until it is a valid VHDL87 or VHDL93 name.
static java.lang.String	makeVHDLPortName(Port port)
static void	msg(java.lang.String msg)
void	openDesignOutputFile()
void	print(java.lang.String s)
void	println(java.lang.String s)
void	setClassmapTable(java.util.Hashtable ht)
void	setDesign(Design design)
void	setOutputDirectory(java.io.File dir)
java.lang.String	tabulate(java.lang.String s, int min_width, int tab_width)
static void	usage()
void	writeComponentDeclaration(SimObject tmp) write a VHDL component declaration for SimObject (or Subdesign) tmp.
void	writeComponentInstantiation(SimObject obj)
void	writeDesign() write a VHDL structural description of the current Design
void	writeDesignArchitecture()
void	writeDesignComponentDeclarations()
void	writeDesignConfiguration()
void	writeDesignEntityDeclaration()
void	writeDesignHeader()
void	writeDesignNetlist()
void	writeDesignPortList(Design design)
void	writeDesignSignalDeclarations()
void	writeIpinConnection(Ipin obj) At the moment, Hades uses separate "Ipin" components as both interactive switches and to indicate hierarchy connections.
void	writeMakefile() write a "makefile" script from the dependency information collected in vhldFilesTable and makefileStack.
void	writeOpinConnection(Opin obj) see the discussion for Ipin
void	writeSimObjectComponentDeclaration(SimObject obj) write a component declaration for SimObject 'obj'.
void	writeSubdesignComponentDeclaration(Design sub)
void	writeSubdesignsAndSimobjects(Design parent)

Methods inherited from class java.lang.Object

clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

VERSION_ID

public static final java.lang.String VERSION_ID

See Also:

Constant Field Values

debug

public static boolean debug

design

Design design

resourceName

java.lang.String resourceName

fileName

java.lang.String fileName

outputDirectory

java.io.File outputDirectory

printWriter

java.io.PrintWriter printWriter

modelFactory

VHDLModelFactory modelFactory

componentDeclTable

java.util.Hashtable componentDeclTable

vhdlFilesTable

java.util.Hashtable vhdlFilesTable

makefileStack

java.util.Stack makefileStack

architectureTable

java.util.Hashtable architectureTable

configurationTable

java.util.Hashtable configurationTable

instanceTable

java.util.Hashtable instanceTable

classmapTable

java.util.Hashtable classmapTable

objectToNameTable

java.util.Hashtable objectToNameTable

nameToObjectTable

java.util.Hashtable nameToObjectTable

dontWritePowerPorts

boolean dontWritePowerPorts

defaultArchitectureName

java.lang.String defaultArchitectureName

defaultConfigurationName

java.lang.String defaultConfigurationName

Constructor Detail

VHDLWriter

public VHDLWriter()

create a new VHDLWriter for a given Hades Design

Method Detail

setClassmapTable

public void setClassmapTable(java.util.Hashtable ht)

getClassmapTable

public java.util.Hashtable getClassmapTable()

setOutputDirectory

public void setOutputDirectory(java.io.File dir)

setDesign

public void setDesign(Design design)

writeDesign

public void writeDesign()

write a VHDL structural description of the current Design

writeSubdesignsAndSimobjects

public void writeSubdesignsAndSimobjects(Design parent)

openDesignOutputFile

public void openDesignOutputFile()

writeDesignHeader

public void writeDesignHeader()

writeDesignEntityDeclaration

public void writeDesignEntityDeclaration()

writeDesignPortList

public void writeDesignPortList(Design design)

writeDesignArchitecture

public void writeDesignArchitecture()

writeDesignComponentDeclarations

public void writeDesignComponentDeclarations()

writeComponentDeclaration

public void writeComponentDeclaration(SimObject tmp)

write a VHDL component declaration for SimObject (or Subdesign) tmp.

Due to the special role of Hades Ipin and Opin connectors, we do not write declarations for these components.

writeSubdesignComponentDeclaration

public void writeSubdesignComponentDeclaration(Design sub)

writeSimObjectComponentDeclaration

public void writeSimObjectComponentDeclaration(SimObject obj)

write a component declaration for SimObject 'obj'. This method doesn't check for double/multiple names after VHDL name mangling.

writeDesignSignalDeclarations

public void writeDesignSignalDeclarations()

getSignalType

public static java.lang.String getSignalType(Signal signal)

writeDesignNetlist

public void writeDesignNetlist()

writeIpinConnection

public void writeIpinConnection(Ipin obj)

At the moment, Hades uses separate "Ipin" components as both interactive switches and to indicate hierarchy connections. Also, the name of the "Ipin" component is uses as the port name, which may (or may not) be different from the signal name connected to the Ipin.

VHDL, on the other hand, uses signals directly - and it does not allow the same name for a component and a signal in one architecure.

To solve this mismatch, we do the following:

1. If the Ipin Component has the same name as the Signal connected to it, this method does only write a comment. In effect, this results in the correct solution: the signal is declared as an input Port to this entity, and used as that in the following code.
2. If the Ipin Component has a different name than the Signal connected to it, we write a signal assignment.

writeOpinConnection

public void writeOpinConnection(Opin obj)

see the discussion for Ipin

writeComponentInstantiation

public void writeComponentInstantiation(SimObject obj)

writeDesignConfiguration

public void writeDesignConfiguration()

getEntityNameFromClassname

public java.lang.String getEntityNameFromClassname(SimObject obj)

construct a valid VHDL entity name for a given SimObject or (Sub)Design. For subdesigns, this method uses the resource name of the subdesign and strips of any extension, e.g. "/hades/examples/simple/dlatch.hds" becomes "hades_examples_simple_dlatch". Next, we check whether our classmapTable has a corresponding key entry. If so, we use the value from classmapTable, else we use the key.

For other SimObjects, we use the SimObject classname as the key to check in classmapTable. If no mapping is found there, we convert the class name to a valid VHDL name by replacing '.' characters with '_' characters.

This algorithm does not currently check for name clashes resulting from upper/lowercase problems. e.g. "hades.models.gates.Inv" becomes "hades_models_gates_Inv".

makeVHDLName

public static java.lang.String makeVHDLName(java.lang.String s)

mangle name s until it is a valid VHDL87 or VHDL93 name. Default is VHDL87, for better tool compatibility.

makeUniqueVHDLName

public java.lang.String makeUniqueVHDLName(Signal s)

makeUniqueVHDLName

public java.lang.String makeUniqueVHDLName(SimObject so)

makeUniqueVHDLName

public java.lang.String makeUniqueVHDLName(java.lang.Object obj,
                                           java.lang.String objName)

makeVHDLPortName

public static java.lang.String makeVHDLPortName(Port port)

getPortDirection

public static java.lang.String getPortDirection(Port port)

getPortSignalType

public static java.lang.String getPortSignalType(Port port)

writeMakefile

public void writeMakefile()

write a "makefile" script from the dependency information collected in vhldFilesTable and makefileStack.

Currently, this simply lists the generated .vhd files in an order suitable for VHDL analysis, with the simobjects (simple models) first, then the subdesigns, and finally the top-level design.

"vhdlan" is used as the program name for the VHDL analyzer. Guess what simulator we have :-)

dumpTables

public void dumpTables()

tabulate

public java.lang.String tabulate(java.lang.String s,
                                 int min_width,
                                 int tab_width)

print

public void print(java.lang.String s)

println

public void println(java.lang.String s)

msg

public static void msg(java.lang.String msg)

dbg

public static void dbg(java.lang.String msg)

usage

public static void usage()

main

public static void main(java.lang.String[] argv)
                 throws java.lang.Exception

check the VHDL output on the Hades Design specified via file/resource name argv[1] and write to the directory specified in argv[0]

Throws:

java.lang.Exception