USART 8251 receiver error detection

Description

This applet demonstrates the three receiver error conditions detected by the USART 8251 chip. These errors are:

• overrun error: indicates that a new data character was received before the previously character was read by the host microprocessor. A data loss occured.
• parity error: set when the parity of an incoming data character does not match the expected value.
• frame error: indicates a missing stop bit. This error can only happen when the communication settings of transmitter and receiver (e.g. baud-rate) don't match, when the connection was lost, or the transmitter is faulty.

Unlike the previous applets, we cannot use the transmitter of the 8251 chip as a source of the RS-232 datastream, because the transmitter only generates correct serial data. Instead, we use the stimuli generator components to supply the receiver first with valid and afterwards with deliberately broken input data. As no output signals are provided to observe the error conditions directly, the status register has to be read to check the error flags. Naturally, the stimuli generator component is also used to first initialize the USART and to control the data-bus interface during the data transfers and status read operations.

The sequence consists of the following steps:

1. After a reset pulse, a first write operation is used to initialize the 8251 mode register with the value 0xfd, which selects asynchronous communication with eight databits, even parity, and two stopbits. Also, the 1X clock-prescaler mode is selected. Obviously, we have to enable parity in order to demonstrate a parity error later on.

2. Next, a value of 0x14 is written to the command register, which enables the on-chip receiver, and also resets the error indicator bits in the status register.

3. A first status register read operation returns the value 0x80. This indicates that the receiver has not yet received any data (D1=0), while the transmitter is disabled (TXRDY or D2=0) and nDRS is asserted (D7=1). The receiver error flags are all cleared.

4. The stimuli generator is now used to generate a valid RS-232 encoding for the eight bit data value 0x55 on the RXD input of the receiver block. Note that the RXRDY status output goes low as soon as the receiver detects the start bit, and goes high again after the receiver has detected a valid stop bit.

5. A read operation of the status register now returns the value 0x82. The RXRDY bit (D1) is now set, which indicates that a data character is waiting in the receive buffer. All error bits are cleared, indicating a successful transmission.

6. A first read operation of the receive buffer returns the data character 0x55. Note that the read operation also automatically resets the RXRDY output (and the RDRDY bit in the status register. However, the data value itself is not cleared from the receive buffer, and another receive buffer read operation would again return the data value (0x55).

7. The stimuli generator is now used to generate the RS-232 encoding for the eight bit data value 0x5A on the RXD input of the receiver block. However, note that the wrong parity is sent after the eight databits. Note that the RXRDY status output goes low as soon as the receiver detects the start bit, and goes high again after the receiver has detected a valid stop bit.

8. A read operation of the status register now returns the value 0x8A. The RXRDY bit (D1) is set again, which indicates that a data character is waiting in the receive buffer. However, the parity-error bit PE (D3) is also set, which means that the received data is probably incorrect. Again, the inverted status of the nDSR input is reported (D7=1).

9. A read operation of the receive buffer returns the received data character 0x5A and resets RXRDY status. Naturally, in general the receiver has no way to know which of the data and parity bits is faulty when a parity error condition is detected. In this case, the data value of 0x5A is correct, because the error was limited to the parity bit.

10. To reset the overrun error bit in the status register, a command write operation with the ER bit set is now performed.

11. The stimuli generator is now used to generate the RS-232 encoding for the eight bit data value 0x57 on the RXD input of the receiver block including the correct even parity bit. However, the RXD input is kept low during the stop bit period. In the Hades simulation model of the 8251, the receiver still asserts RXRDY despite the missing stop bit. However, the framing-error bit in the status register is also set.

12. A read operation of the status register now returns the value 0xA2. The RXRDY bit (D1) is set again, which indicates that a data character is waiting in the receive buffer. However, the framing-error bit PE (D5) is now set, which indicates a missing stop bit and as such a synchronization failure between transmitter and receiver. Again, the inverted status of the nDSR input is reported (D7=1).

13. A read operation of the receive buffer returns the received data character 0x57 and resets RXRDY status.

14. To reset the overrun error bit in the status register, a command write operation with the ER bit set is now performed.

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