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DescriptionA demonstration of byte- and word-based addressing schemes.
The question of the addressing scheme arises in all microprocessor
systems, when the native word-width of the processor is not 8 bits.
Here, a word-width of 16 bits is chosen,
while most current systems are based on 32 bit processors.
The circuit consists of two ROM memories of 256 words of 16 bits each.
Therefore, each ROM component has a 16 bit data output port
and a 8 bit address input port.
Both ROMs are initialized with the same data,
namely a linear sequence (i.e. ROM(addr) = addr).
Open the memory editors (popup-menu, edit-component) to see the
memory contents.
Again, the ROM memory editor highlights the last accessed memory cell
in green color.
. Naturally, one can just connect the address bus to the address inputs of all memories. This strategy is called word-addressing and is illustrated by the ROM on the right, where the lower 8 bits of the address bus (7:0) are connected to the address input of the ROM. Incrementing the address by one will select the next data word from the memory.
The left ROM shows the strategy called byte-addressing. Here, the bits it indices 8:1 from the address bus are connected to the address input of the ROM (bit 0 is discarded). Incrementing the address bus value by two will select the next word from the ROM. (Naturally, the lower two bits of the address bus would be discarded for a 32-bit system, and the lower three bits would be discarded in a 64-bit system).
In this scheme, multiple choices exist as how to handle misaligned memory accesses. A misaligned memory access occurs when the lower bit(s) of the address value or non-zero. Most systems interpret a misaligned memory address as a program bug and abort program execution (one reasons of the dreaded "segmentation violation" on Windows systems). Another alternative is to interpret the address as a valid byte address and to return the corresponding data. This means to read two memory words and re-assemble the corresponding value from both data words. Due to the complexity, this scheme is rarely used.
address so that the output bus of t
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