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RAM address decoder (2 to 4 bit with enable)

RAM address decoder (2 to 4 bit with enable) screenshot

Description

The address decoder required for the simple 4x4 bit random access memory circuit. While nChipSelect is high, all word-lines are disabled. When nChipSelect is low, the decoder decodes the 2-bit input on the A1,A0 input lines and enables the corresponding word-line.

When the number of memory addresses becomes very large, the addresses are usually split into multiple parts, each of which is decoded separately. For example, a 64 Mbit RAM organized as 2 M words of 32 bits might include 1024 blocks of 512 wordlines of 128 bits. Then, a first 10-to-1024 decoder would enable one of the 1024 blocks, while a second 9-to-512 decoder enables one of the 512 wordlines of the selected block, and a third stage of 2-to-4 decoders selects one 32-bit group out fo the 128-bits of the block. This organization avoids very long bitlines, which are limited to at most a thousand connections due to electrical effects. Naturally, each block requires its own second-level (here 9-to-512) and third-level (here 2-to-4) decoders, unless it is possible to share the second-level decoders between a few blocks. (Note that one 10-to-1024 decoder and 1024 9-to-512 decoders plus 1024 2-to-4 decoders are not more expensive than a single impractical 21-to-2million decoder!).

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Impressum | 24.11.06
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/40-memories/40-ram/ram-decoder24_print.html