The counter consists of two separate stages of a single JK-flipflop (1:2) and three JK-flipflops (1:8, asynchronous). The reset inputs (R01 and R02) are shared by all flipflops.
For the full 1:16 counter, the output of the first stage QA is connected to the clock input nB of the 1:8 counter stage.
Larger (asynchronous) binary counters can be built by a cascade of multiple 7493 chips.
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