The counter consists of two separate stages of a single JK-flipflop (1:2) and three JK-flipflops (1:6, asynchronous). The reset inputs (R01 and R02) are shared by all flipflops.
For the full 1:12 counter, the output of the first stage QA is connected to the clock input nB of the 1:6 counter stage. Note the counting sequence 0,1,2,4,5,6 of the 1:6 counter. This was probably preferred over the 0,1,2,3,4,5 sequence due to its cheaper implementation (note that no additional gates are required in front of the JK-flipflops).
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