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Description
An array multiplier to calculate the square of the 4-bit input. The circuit example is taken from (I.V.Klotchkov and S.Pedersen, A Codesign Case Study: Implementing Arithmetic Functions in FPGAs, Proc. ECBS96, p.389-395) who in turn reference (K.Hwang, Computer Arithmetic: Principles, Architectures, and Design, Wiley, 1979).
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