Carry-lookahead adder (16 bit)

Description

This circuit demonstrates the modular 16-bit carry-lookahead adder presented in Hennessy and Patterson, Computer Architecture, 1995. Please consult the book for a detailed description of the circuit and a discussion of performance and implementation cost.

The adder consists of 16 1-bit adder blocks and a tree of (8+4+2+1) carry lookahead blocks, which are realized as Hades subdesigns called sum.hds and cla.hds. Both the adder and the CLA are available as separate applets, but you can also just select the "edit" operation in the applet schematics to open the selected subdesign block in a new editor window.

The circuit schematics consists of five rows of related components. The top row consists of 16 LEDs and Hex displays that show the current output value of the adder. Below that are the two rows of 16 input switches for the A (A15..A0) and B (B15..B0) inputs. Below the switches is the row of the adder blocks, each of which connects on its top side to its corresponding Ai and Bi inputs and the Si sum bit. Below the adders is the tree of the carry lookahead generator blocks, whose connections are also illustrated in the bottom right corner. For layout reasons, the carry input switch is also located in the bottom right corner, because it is logically equivalent to the A0 and B0 inputs to the rightmost (least significand) adder.

The advantage of the CLA scheme used in this circuit is its simplicity, because each CLA block calculates the generate and propagate signals for two bits only. This is much easier to understand than the more complex variants presented in other textbooks, where combinatorical logic is used to calculate the G and P signals of four or more bits, and the resulting adder structure is slightly faster but also less regular.

Exercise: Explain and design the missing logic to calculate the carry-out bit of the adder.

Run the applet | Run the editor (via Webstart)