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Master-slave JK-flipflop with reset

Master-slave JK-flipflop with reset screenshot


This circuit shows a typical master-slave JK-flipflop, built from two basic D-type NAND-latches. While JK-flipflops are not used very often in modern integrated circuits, they were very popular during the TTL era of circuit design because of their flexibility. With a few additional gates in front of the J and K inputs, a JK flipflop can emulate most other types of flipflops including D-flipflops and T-flipflops. JK flipflops are also very convenient to construct counters.

Warning: It is hard to initalize this circuit, but that is intentional. Either play with the input switches (including the NRESET switch) and try to initialize the circuit, or read the detailed explanation below and follow the instructions. You can also step to the next applet, which also demonstrates the JK-flipflop, but uses different simulation models and a very different modeling approach.

Even a first glance at the circuit schematics shows that the flipflop consists of two almost identical D-latch structures. However, while the master latch on the left is directly controlled by the clock signal, the slave latch on the right is controlled by the inverted clock signal.

This architecture leads to the following behavior: At the rising edge of the clock signal, the J and K input values are propagated to and stored in the master flipflop, while the slave flipflop (which is controlled by the inverted clock) remains unchanged. On the falling edge of the clock signal, the output values of the master flipflops are propagated to and stored in the slave flipflop, which in turn drives the flipflop Q and NQ outputs.

Note: This circuit also illustrates a very important modelling aspect of digital simulation and the std_logic logic model, namely that the feedback paths in the flipflop circuit make it very difficult to initialize the flipflop after the simulation is started. The point is that all gates and the switches are initialized to the undefined U value which dominates all other logical values. Therefore, as soon as you have initialized a gate in the circuit, the new output values of those gates trigger other gates which still have one (or more) U inputs, resulting in U inputs for those other gates. Sooner or later, those U values propagate to the recently initialized gates, resetting them to the undefined value.

The only way to initialize this circuit at all is to use the additional NRESET input switch: First, click the J, K, and CLK inputs until all switches are set to the active 1 state, and then set NRESET to 0 to initialize the flipflop. After all wires and gates in the flipflop have non-U values, set NRESET to 1 to begin playing with the circuit.

Another problem you might encounter while playing with the circuit are oscillations. Such oscillations can occur when input signals are toggled while the circuit has not yet reached a stable state (in other words, setup and hold time violations), resulting in hazards that propagate (repeatedly) through the circuit. Those oscillations are artifacts of the discrete event simulation algorithm and usually do not occur in real hardware. Instead, the transistors in real gates enter a metastable state, where the cross-coupled transistors are outside their digital operating conditions for possibly very long times. While the gates will finally settle for a well-defined output value, this output value can be either 0 or 1, and cannot be predicted.

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Impressum | 24.11.06