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Multiplexer circuits (2:1 and 4:1)DescriptionThis applet shows the
two-level AND-OR implementation of the 2:1 and 4:1 multiplexors.
Each AND gate has (2^n + 1) inputs, the first of which is connected
to one of the data inputs of the multiplexer.
Each one of the remaining AND gates is connected in a binary pattern
to either the direct or the inverted control inputs of the multiplexer.
This structure implies that only the AND gate corresponding to the
current input values on the control inputs will have its
lower (n-1) inputs high, so that it transmits its data input value.
All other AND gates have at least one low input value and are disabled.
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Impressum | 24.11.06