Package hades.models.rtlib.logic

Class Summary
And And - the logical AND of all bits in this SignalStdLogicVector which results in a StdLogic1164 output value.
BitwiseAnd BitwiseAnd - the logical bitwise AND of buses A and B Signals are expected to be SignalStdLogicVector objects.
BitwiseNot BitwiseNot - the logical bitwise negation if input A.
BitwiseOr BitwiseOr - the logical bitwise OR of buses A and B Signals are expected to be SignalStdLogicVector objects.
BitwiseXor BitwiseXor - the logical bitwise OR of buses A and B Signals are expected to be SignalStdLogicVector objects.
GenericOnebitLogicObject GenericOnebitLogicObject - the utility base class for HADES n-to-1 bit logical RTLIB models,
N1And N1And - the logical bitwise AND of bus B and n copies of input value A.
N1Or N1Or - the logical bitwise OR of bus B and n copies of input value A.
Nand Nand - the logical NAND of all bits in this SignalStdLogicVector which results in a StdLogic1164 output value.
Nor Nor - the logical NOR of all bits in this SignalStdLogicVector which results in a StdLogic1164 output value.
Or Or - the logical OR of all bits in SignalStdLogicVector A which results in StdLogic1164 output Y.
Xnor Xnor - the logical XNOR (= even parity) of all bits in this SignalStdLogicVector which results in a StdLogic1164 output value.
Xor Xor - the logical XOR (= odd parity) of all bits in this SignalStdLogicVector which results in a StdLogic1164 output value.