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Class Summary |
| CounterRE |
CounterRE: abstract base class for n-bit positive-edge triggered
counters with enable and reset. |
| CounterRE16 |
CounterRE16: an 16-output positive edge-triggered counter with nreset
and enable inputs, and carry output. |
| CounterRE8 |
CounterRE8: an 8-output positive edge-triggered counter with nreset
and enable inputs, and carry output. |
| LFSRAnalyzer |
LFSRAnalyzer: abstract base class for a 32-bit LFSR pseudorandom
signature analyzer based on the (31 3 0) polynom. |
| LFSRAnalyzer16 |
LFSRAnalyzer16:
an 16-input LFSR signature analyzer based on the (31 3 0) polynom,
where the lower 16 bits of the LFSR are used for the inputs. |
| LFSRAnalyzer24 |
LFSRAnalyzer24:
an 24-input LFSR signature analyzer based on the (31 3 0) polynom,
where the lower 24 bits of the LFSR are used for the inputs. |
| LFSRAnalyzer32 |
LFSRAnalyzer32:
an 32-input LFSR signature analyzer based on the (31 3 0) polynom,
where the lower 32 bits of the LFSR are used for the inputs. |
| LFSRAnalyzer8 |
LFSRAnalyzer8:
an 8-input LFSR signature analyzer based on the (31 3 0) polynom,
where the lower 8 bits of the LFSR are used for the inputs. |
| LFSRGenerator |
LFSRGenerator: abstract base class for LFSR pseudorandom value generators
based on the (31 3 0) polynom. |
| LFSRGenerator16 |
LFSRGenerator16: an 16-output LFSR generator based on the (31 3 0) polynom,
where the lower 16 bits of the LFSR are used for the outputs. |
| LFSRGenerator24 |
LFSRGenerator24: an 24-output LFSR generator based on the (31 3 0) polynom,
where the lower 24 bits of the LFSR are used for the outputs. |
| LFSRGenerator32 |
LFSRGenerator32: an 32-output LFSR generator based on the (31 3 0) polynom,
where the lower 32 bits of the LFSR are used for the outputs. |
| LFSRGenerator8 |
LFSRGenerator8: an 8-output LFSR generator based on the (31 3 0) polynom,
where the lower 8 bits of the LFSR are used for the outputs. |
| Register |
Register - a simple subclass of SimObject that models a n-bit
rising-edge triggered, editable D-register without reset
or enable. |
| RegisterR |
RegisterR - a simple subclass of Register that models a n-bit
rising-edge triggered, editable D-register with reset. |
| RegisterRE |
RegisterRE - a simple subclass of Register that models a n-bit
rising-edge triggered, editable D-register with reset and enable. |
| ShiftRegister |
ShiftRegister - a simple subclass of Register that models a n-bit
rising-edge triggered, editable D-register with reset
and right-shift. |