|
Class Summary |
| AccessMemory |
Handle memory and cache accesses with one class which dispatches
the different requests to the different MipsMemories
Tasks performed by this class:
- static address translation
- call of dynamic address translation
- decision wether and which caches should be used
- modify partial word accesses to word accesses
- provide Memory interface to give access to the full virtual
address space |
| AdrTrans |
Static address translation needed for usage of MipsMemory |
| Cache |
Implementation of the data cache, non associative, line size
of 1 word, variable cache size. |
| DataCache |
Implementation of the data cache, non associative, line size
of 1 word, variable cache size. |
| FastAccessMemory |
Do the same like AccessMemory - without the layers below for
fast operation |
| HadesInterface |
Upper part of the HADES interface: State machine for memory access |
| IDTR3051 |
Lower part of the HADES interface: Port handling |
| InstrCache |
Implementation of the instr cache, non associative, line size
of 1 word, variable cache size. |
| MemoryDispatcher |
This class seperates the physical address space into 64K segments
each of 64K (bytes) size. |
| MemoryManagementUnit |
Address translation |
| NullMemory |
This MipsMemory ignores every write access and always returns
0 on read requests. |
| SmartIDTR3051 |
Lower part of the HADES interface: Port handling |
| TinyBPMemory |
Memory implementation as a simple array with no wait states. |
| TinyMemory |
Memory implementation as a simple array with no wait states. |