#FIG 3.2 Landscape Center Metric A4 100.0 Single -2 1200 2 0 32 #cccccc 0 33 #666666 0 34 #4193ff 0 35 #008000 0 36 #004000 0 37 #600000 0 38 #9f9f9f 0 39 #ff6060 0 40 #ff6060 0 41 #cccccc 0 42 #dab800 0 43 #b79b73 0 44 #4193ff 0 45 #007fff 0 46 #008fff 0 47 #009fff 0 48 #00afff 0 49 #00bfff 0 50 #00cfff 0 51 #00dfff 0 52 #00efff 0 53 #0fffef 0 54 #1fffdf 0 55 #2fffcf 0 56 #3fffbf 0 57 #4fffaf 0 58 #5fff9f 0 59 #6fff8f 0 60 #7fff7f 0 61 #8fff6f 0 62 #9fff5f 0 63 #afff4f 0 64 #bfff3f 0 65 #cfff2f 0 66 #dfff1f 0 67 #efff0f 0 68 #ffef00 0 69 #ffdf00 0 70 #ffcf00 0 71 #ffbf00 0 72 #ffaf00 0 73 #ff9f00 0 74 #ff8f00 0 75 #ff7f00 0 76 #ff6f00 0 77 #ff5f00 0 78 #ff4f00 0 79 #ff3f00 0 80 #ff2f00 0 81 #ff1f00 0 82 #ff0f00 0 83 #ef0000 0 84 #df0000 0 85 #cf0000 0 86 #bf0000 0 87 #af0000 0 88 #9f0000 0 89 #8f0000 0 90 #7f0000 0 91 #dcdcdc 0 92 #ff0400 0 93 #ff0800 0 94 #ff0c00 0 95 #ff1000 0 96 #ff1400 0 97 #ff1800 0 98 #ff1c00 0 99 #ff2000 0 100 #ff2400 0 101 #ff2800 0 102 #ff2c00 0 103 #ff3000 0 104 #ff3400 0 105 #ff3800 0 106 #ff3c00 0 107 #ff4000 0 108 #ff4400 0 109 #ff4800 0 110 #ff4c00 0 111 #ff5000 0 112 #ff5400 0 113 #ff5900 0 114 #ff5d00 0 115 #ff6100 0 116 #ff6500 0 117 #ff6900 0 118 #ff6d00 0 119 #ff7100 0 120 #ff7500 0 121 #ff7900 0 122 #ff7d00 0 123 #ff8100 0 124 #ff8500 0 125 #ff8900 0 126 #ff8d00 0 127 #ff9100 0 128 #ff9500 0 129 #ff9900 0 130 #ff9d00 0 131 #ffa100 0 132 #ffa500 0 133 #ffaa00 0 134 #ffae00 0 135 #ffb200 0 136 #ffb600 0 137 #ffba00 0 138 #ffbe00 0 139 #ffc200 0 140 #ffc600 0 141 #ffca00 0 142 #ffce00 0 143 #ffd200 0 144 #ffd600 0 145 #ffda00 0 146 #ffde00 0 147 #ffe200 0 148 #ffe600 0 149 #ffea00 0 150 #ffee00 0 151 #fff200 0 152 #fff600 0 153 #fffa00 0 154 #fffa00 3 0 0 1 0 7 25 0 -1 0 0 1 0 6 3 1 1.0 48.00 144.00 4950 4500 5850 4725 6300 4500 6300 3487 5850 3262 4725 3375 0.0000 1.0000 1.0000 1.0000 1.0000 0.0000 2 4 0 1 0 8 25 0 38 0 0 0 6 0 0 5 4162 5287 5962 5287 5962 5737 4162 5737 4162 5287 2 4 0 1 0 8 25 0 38 0 0 0 6 0 0 5 1462 5287 3262 5287 3262 5737 1462 5737 1462 5287 2 2 0 1 0 8 25 0 38 0 0 0 0 0 0 5 4162 6187 5962 6187 5962 7087 4162 7087 4162 6187 2 2 0 1 0 8 25 0 38 0 0 0 0 0 0 5 1462 6187 3262 6187 3262 7087 1462 7087 1462 6187 2 4 0 1 0 8 25 0 38 0 0 0 6 0 0 5 3487 7537 5287 7537 5287 7987 3487 7987 3487 7537 2 4 0 1 0 8 25 0 38 0 0 0 6 0 0 5 1462 7537 3262 7537 3262 7987 1462 7987 1462 7537 2 4 0 1 0 18 25 0 38 0 0 0 12 0 0 5 1350 2250 3150 2250 3150 2700 1350 2700 1350 2250 2 2 0 1 0 8 25 0 37 0 0 0 0 0 0 5 2250 4050 4950 4050 4950 4950 2250 4950 2250 4050 2 4 0 1 0 12 24 0 37 1.00 0 0 9 0 0 5 2475 2925 4725 2925 4725 3600 2475 3600 2475 2925 2 4 0 1 0 8 24 0 39 0 0 0 9 0 0 5 4050 5400 5850 5400 5850 5850 4050 5850 4050 5400 2 4 0 1 0 8 24 0 39 0 0 0 9 0 0 5 1350 5400 3150 5400 3150 5850 1350 5850 1350 5400 2 2 0 1 0 8 24 0 39 0 0 0 0 0 0 5 1350 6300 3150 6300 3150 7200 1350 7200 1350 6300 2 2 0 1 0 8 24 0 39 0 0 0 0 0 0 5 4050 6300 5850 6300 5850 7200 4050 7200 4050 6300 2 4 0 1 0 8 24 0 39 0 0 0 9 0 0 5 1350 7650 3150 7650 3150 8100 1350 8100 1350 7650 2 1 0 1 0 30 24 0 38 0 0 0 9 1 0 2 3 1 1.0 57.00 144.00 3600 3600 3600 4050 2 1 0 1 0 30 24 0 38 0 0 0 9 1 0 2 3 1 1.0 57.00 144.00 2250 7200 2250 7650 2 4 0 1 0 8 24 0 39 0 0 0 9 0 0 5 3375 7650 5175 7650 5175 8100 3375 8100 3375 7650 2 1 0 1 0 30 24 0 38 0 0 0 9 1 0 2 3 1 1.0 57.00 144.00 4837 7200 4275 7650 2 4 0 1 0 18 24 0 38 0 0 0 6 0 0 5 5400 7312 7200 7312 7200 7762 5400 7762 5400 7312 4 1 0 5 0 16 15.0 0.0 4 316.0 2250.0 3600 3374 Spezifikation (SDL)\001 4 0 0 5 0 16 18.0 0.0 4 366.0 2433.0 9000 5175 Vorgabe HW/SW \001 4 0 0 5 0 16 18.0 0.0 4 366.0 3866.0 9000 3375 mehrere Prozesse/Threads\001 4 0 0 5 0 16 18.0 0.0 4 366.0 2916.0 9000 2925 SDL, StateCharts, ...\001 4 0 0 5 0 16 18.0 0.0 4 366.0 4266.0 8100 6750 Partitionierung und Synthese:\001 4 0 0 5 0 16 18.0 0.0 4 366.0 3816.0 8100 4500 diverse Randbedingungen:\001 2 1 0 1 0 0 5 0 -1 0 0 0 12 0 0 2 450 1125 13050 1125 2 1 0 1 0 0 5 0 -1 0 0 0 12 0 0 2 450 9000 13050 9000 2 2 0 1 7 0 5 0 -1 0 0 0 0 0 0 5 0 0 13500 0 13500 9450 0 9450 0 0 4 1 0 5 0 16 15.0 0.0 4 316.0 350.0 2250 7987 SW\001 4 1 0 5 0 16 15.0 0.0 4 316.0 1066.0 4950 6975 Synthese\001 4 1 0 5 0 16 15.0 0.0 4 316.0 1300.0 4950 6693 High-Level\001 4 1 0 5 0 16 15.0 0.0 4 316.0 1316.0 4950 5737 HW (VHDL)\001 2 1 0 1 0 0 5 0 -1 0 0 0 9 1 0 2 3 1 1.0 57.00 144.00 4950 5850 4950 6300 2 1 0 1 0 0 5 0 -1 0 0 0 9 1 0 2 3 1 1.0 57.00 144.00 2250 5850 2250 6300 2 1 0 1 0 0 5 0 -1 0 0 0 9 1 0 2 3 1 1.0 57.00 144.00 4050 4950 4950 5400 2 1 0 1 0 0 5 0 -1 0 0 0 9 1 0 2 3 1 1.0 57.00 144.00 3150 4950 2250 5400 4 1 0 5 0 16 15.0 0.0 4 316.0 1433.0 2250 6693 Compilation\001 4 1 0 5 0 16 15.0 0.0 4 316.0 766.0 2250 5737 SW (C)\001 4 1 0 5 0 16 15.0 0.0 4 316.0 1866.0 2250 6975 Codeerzeugung\001 4 1 0 5 0 16 15.0 0.0 4 316.0 1750.0 3600 4781 Partitionierung\001 4 1 0 5 0 16 15.0 0.0 4 316.0 2683.0 3600 4442 Leistungsabsch\344tzung\001 2 1 0 1 0 7 5 0 -1 0 0 0 12 1 0 2 3 1 1.0 57.00 144.00 3600 2250 3600 2925 4 1 0 5 0 16 15.0 0.0 4 316.0 400.0 4275 7987 HW\001 2 1 0 1 0 7 5 0 20 0 0 0 12 1 0 2 3 1 1.0 57.00 144.00 5062 7200 5400 7425 2 1 0 1 0 7 5 0 -1 0 0 0 12 1 0 2 3 1 1.0 57.00 144.00 2700 2700 2925 2925 4 0 0 5 0 16 18.0 0.0 4 366.0 3950.0 8100 2250 eine zentrale Spezifikation:\001 4 0 0 5 0 16 18.0 0.0 4 366.0 2433.0 9000 3825 Zeitbedingungen\001 4 0 0 5 0 16 18.0 0.0 4 366.0 1000.0 9000 5625 Kosten\001 4 0 0 5 0 16 18.0 0.0 4 366.0 1716.0 9000 6075 Zeitplanung\001 4 0 0 5 0 16 18.0 0.0 4 366.0 1366.0 9000 7875 interaktiv\001 4 0 0 5 0 16 18.0 0.0 4 366.0 2283.0 9000 7425 vollautomatisch\001 4 1 0 5 0 16 15.0 0.0 4 316.0 1383.0 2250 2587 Constraints\001 6 3712 1744 3487 2137 2 1 0 1 0 7 5 0 -1 0 0 0 12 0 0 2 3600 2025 3712 2137 2 1 0 1 0 7 5 0 -1 0 0 0 12 0 0 3 3600 1856 3600 2025 3487 2137 2 1 0 1 0 7 5 0 -1 0 0 0 12 0 0 2 3487 1912 3712 1912 1 1 0 1 0 7 5 0 -1 0 1 0.0 3600 1800 56 56 3544 1744 3656 1856 -6 4 0 0 5 0 16 15.0 0.0 4 316.0 1150.0 3825 2025 Entwerfer\001 4 2 0 5 0 16 15.0 0.0 4 316.0 750.0 3375 2025 Kunde\001 4 1 0 5 0 16 15.0 0.0 4 316.0 1500.0 6300 7650 HW Prototyp\001 4 0 0 0 0 1 35.0 0.0 4 700.0 8416.0 1350 900 Codesign: design-flow (ideal)\001 4 0 0 0 0 16 11.0 0.0 4 233.0 2566.0 1350 9330 Systemsimulation - 10.02.99\001 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 2812 56 56 8494 2756 8606 2868 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 3262 56 56 8494 3206 8606 3318 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 3712 56 56 8494 3656 8606 3768 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 5062 56 56 8494 5006 8606 5118 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 5512 56 56 8494 5456 8606 5568 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 5962 56 56 8494 5906 8606 6018 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 7762 56 56 8494 7706 8606 7818 1 1 0 1 0 0 0 0 20 0 1 0.0 8550 7312 56 56 8494 7256 8606 7368