; input.asm
; add & sub with keyboard
init:
 FIM R0R1, 0      ; rom 0
 FIM R2R3, 1      ; rom 1
 FIM RERF, 0      ; ram 0, bank 0
 LDM 8
 XCH R5           ; store input filter
begin:
 LDM 0
 XCH R8
 SRC 1
pull:
 RDR
 JCN NZ, checkNew ; key down
 LD R6
 JCN Z, pull
 LDM 0            ; key released
 XCH R6
 JUN pull
checkNew:
 LD R6
 JCN NZ, pull     ; no new key 
 LDM 1
 XCH R6
execKey:
 RDR
 XCH R4
 LD R5            ; copy filter
 XCH R7
 LD R4
 SUB R7           ; remove ACK
 KBP
 XCH R7
loop:
 LD R7
 JCN Z, getDigit
 DAC
 CLC
 XCH R7
 LDM 4
 ADD R8
 XCH R8
 JUN loop
getDigit:
 SRC 0
 RDR
 KBP
 ADD R8
 XCH R8
 SRC 7
 LD R8            ; copy digit
 XCH R7
 LDM 9
 SUB R7
 XCH R7
 LD R7
 JCN NC, specKey  ; special key?
 LD R9
 JCN NZ, begin    ; bank full?
 LD R8            ; write digit
 WRM
 INC RF           ; next address
 TCC              ; store carry
 XCH R9 
 JUN begin
specKey:
 LD R7
 CMA
 IAC
 XCH 7
 LD RF            ; write length
 WR0
 JMS action
 JCN NZ, chBank   ; add - next bank
 JMS action
 JCN NZ, opSub    ; sub
 JMS action
 JCN NZ, calc     ; calculate?
 JMS action
 JCN NZ, clear    ; clear bank?
 JMS action
 JCN NZ, reset    ; clear all?
action:
 LD R7
 DAC
 JCN Z, found
 XCH R7
 BBL 0
found:
 BBL 1
chBank:
 LD RE
 JCN NZ, begin
 LD R7            ; store operation
 WR2
 FIM RERF, 1
 JUN begin
opSub:
 LDM 2            ; new op-Code
 XCH R7
 JUN chBank       ; next bank
calc:
 LD RE
 JCN Z, begin     ; only one operand
 LDM 2
 XCH RE
 JMS clBank
 LDM 0
 XCH RF
 JMS 256
 JUN reset
clear:
 JMS clBank
 LDM 0
 XCH RF
 JUN begin
reset:
 LDM 0            ; bank 0
 XCH RE
 JMS clBank
 INC RE           ; bank 1
 JMS clBank
 JUN init
doAdd:
 JUN begin
doSub:
 JUN begin
clBank:
 SRC 7
 RD0              ; read length
 JCN NZ doClear
 BBL 0            ; nothing to do
doClear:
 XCH R7
 LDM 0            ; reset address
 XCH RF
loop2:
 SRC 7
 LDM 0            ; clear digits
 WRM
 LD R7
 DAC
 JCN Z, endClear
 XCH R7
 INC RF
 JUN loop2
endClear
 LDM 0            ; clear length
 WR0
 WR1
 WR2
 BBL 0