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Circuit Description

This applet shows the internal gate-level circuit used in the TTL-series 7485 4-bit magnitude comparator ICs. In the first level of logic, using the NAND and AND-OR-INVERT gates, the corresponding bits of the A and B inputs are compared. (This could also have been implemented with XOR gates.) These signals are then ANDed together with the A=B_in input signal to calculate the A=B_out signal.

The second, complex looking stage of the schematics acually consists of two symmetrical circuits, one of which checks for A>B and the other one for B>A. The path from the carry/cascade inputs to the outputs goes through two gates only, resulting in a fast cascade when many circuits are interconnected.