hades.models.rtlib.memory
Class DPRAM

java.lang.Object
  extended byhades.simulator.SimObject
      extended byhades.models.rtlib.memory.GenericMemory
          extended byhades.models.rtlib.memory.DPRAM
All Implemented Interfaces:
java.lang.Cloneable, ContextToolTip, Memory, java.io.Serializable, Simulatable

public class DPRAM
extends GenericMemory

DPRAM - a generic dual-port RAM with n words by m bits. The DPRAM is asymmetric, with port0 being read/write and port1 read-only. It has a global active-low chip-select and an level-sensitive asynchronous write enable. When chip-select is high, both data outputs of the DPRAM are tristated and writes are ignored. This component models a standard MSI/LSI DPRAM with asynchronous write enable - the adresses are never latched. As long as write enable is low, the input data is written to the currently selected address.

Note that the model currently does not check for timing violations during write cycles.

See Also:
Serialized Form

Field Summary
protected  PortStdLogicVector port_A0
           
protected  PortStdLogicVector port_A1
           
protected  PortStdLogicVector port_DI0
           
protected  PortStdLogicVector port_DO0
           
protected  PortStdLogicVector port_DO1
           
protected  PortStdLogic1164 port_nCS
           
protected  PortStdLogic1164 port_nWE
           
static double t_access
           
static double t_min_we_cycle
           
static double t_setup
           
static double t_tristate
           
static double t_undefined
           
 
Fields inherited from class hades.models.rtlib.memory.GenericMemory
bit_mask, data, enableAnimationFlag, last_read_addr, last_read_data, last_write_addr, last_write_data, MEF, n_bits, n_words, resourcename, TRISTATED, UNDEFINED, vector_000, vector_111, vector_UUU, vector_XXX, vector_ZZZ
 
Fields inherited from class hades.simulator.SimObject
classloader, console, debug, editor, name, parent, ports, propertySheet, simulator, symbol, versionId, visible
 
Constructor Summary
DPRAM()
          DPRAM constructor
 
Method Summary
 boolean canChangeSize()
           
protected  void constructPorts()
           
 void elaborate(java.lang.Object arg)
          elaborate(): On elaboration, the inputs of the DPRAM will be undefined.
 void evaluate(java.lang.Object arg)
          evaluate(): If either port_nCS or port_nWE are undefined, the DPRAM data is invalidated, and the DO1 value is undefined.
 boolean resize(int n_words, int n_bits)
           
 void setBitsPerWord(int n_bits)
           
 void setSize(int n_words)
           
 
Methods inherited from class hades.models.rtlib.memory.GenericMemory
addMemoryListener, addMemoryListenerOld, checkInvalidateMemory, configure, constructStandardValues, createMemory, dataAtAddressIsUndefined, dbg, getAddressBusWidth, getAddrOffset, getBitsPerWord, getConfigDialog, getDataArray, getDataAt, getEnableAnimationFlag, getExternalResources, getHexDigitsPerWord, getHexString, getInstructionDecoder, getPropertySheet, getResourcename, getSize, getToolTip, initialize, initializeWithDefaultValues, initializeWithRandomValues, initializeWithX, initializeWithZeroes, isConnected, main, merge, needsExternalResources, notifyReadListeners, notifyReadListenersOld, notifyWriteListeners, notifyWriteListenersOld, parse, parseLabelLine, parseRAM, removeMemoryListener, removeMemoryListenerOld, save, setDataArray, setDataAt, setEnableAnimationFlag, setEnableAnimationFlag, setInstructionDecoder, setResourcename, toString, warning, write
 
Methods inherited from class hades.simulator.SimObject
constructDynamicSymbol, copy, getBindkey, getClassLoader, getDebug, getEditor, getFullName, getName, getParent, getPort, getPorts, getResourceAsStream, getSimulator, getSymbol, getSymbolResourceName, getVersionId, isVisible, keyPressed, message, mousePressed, needsDynamicSymbol, setClassLoader, setConsole, setDebug, setEditor, setName, setParent, setPorts, setSimulator, setSymbol, setVersionId, setVisible, tearDown
 
Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, wait, wait, wait
 

Field Detail

port_A0

protected PortStdLogicVector port_A0

port_A1

protected PortStdLogicVector port_A1

port_DI0

protected PortStdLogicVector port_DI0

port_DO0

protected PortStdLogicVector port_DO0

port_DO1

protected PortStdLogicVector port_DO1

port_nWE

protected PortStdLogic1164 port_nWE

port_nCS

protected PortStdLogic1164 port_nCS

t_access

public static final double t_access
See Also:
Constant Field Values

t_tristate

public static final double t_tristate
See Also:
Constant Field Values

t_undefined

public static final double t_undefined
See Also:
Constant Field Values

t_setup

public static final double t_setup
See Also:
Constant Field Values

t_min_we_cycle

public static final double t_min_we_cycle
See Also:
Constant Field Values
Constructor Detail

DPRAM

public DPRAM()
DPRAM constructor

Method Detail

constructPorts

protected void constructPorts()
Overrides:
constructPorts in class GenericMemory

canChangeSize

public boolean canChangeSize()
Specified by:
canChangeSize in interface Memory
Overrides:
canChangeSize in class GenericMemory

setSize

public void setSize(int n_words)
Specified by:
setSize in interface Memory
Overrides:
setSize in class GenericMemory

setBitsPerWord

public void setBitsPerWord(int n_bits)
Specified by:
setBitsPerWord in interface Memory
Overrides:
setBitsPerWord in class GenericMemory

resize

public boolean resize(int n_words,
                      int n_bits)
Specified by:
resize in interface Memory
Overrides:
resize in class GenericMemory

elaborate

public void elaborate(java.lang.Object arg)
elaborate(): On elaboration, the inputs of the DPRAM will be undefined. Correspondingly, the outputs are, too.

Specified by:
elaborate in interface Simulatable
Overrides:
elaborate in class GenericMemory

evaluate

public void evaluate(java.lang.Object arg)
evaluate(): If either port_nCS or port_nWE are undefined, the DPRAM data is invalidated, and the DO1 value is undefined. If port_nCS is high, the DPRAM is inactive. That is, the outputs are tristated, and all write requests are ignored. If port_nCS is low, the output is driven with the memory contents of the currently active address. Also, as long as port_nWE is low, the input data is written to the active address.

Warning: The DPRAM model currently does not check for timing violations or address glitches during write cycles. Instead, the corresponding memory locations are written.

Specified by:
evaluate in interface Simulatable
Overrides:
evaluate in class GenericMemory